1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device with embedded semiconductor memory device of a large storage capacity. More particularly, the present invention relates to a configuration of a row-related control circuit controlling a row select operation in a clock synchronous DRAM (dynamic random access memory) transferring data in synchronization with a clock signal.
2. Description of the Background Art
FIG. 24 is a diagram schematically showing an overall configuration of a conventional semiconductor memory device. In FIG. 24, the semiconductor memory device includes: a plurality of sub-memory arrays SMA0 to SMA3; row decoders RD0 to RD3 provided corresponding to respective sub-memory arrays SMA0 to SMA3 and each selecting a row of a corresponding sub-memory array; a column decoder CDA provided corresponding to sub-memory arrays SMW0 and SMA2 to generate a column select signal selecting a column of sub-memory arrays SMA0 and SMA2; a column decoder CDB provided corresponding to sub-memory arrays SMA1 and SMA3 to generate a column select signal selecting a column of sub-memory arrays SMA1 and SMA3; a data path DPA for supplying/receiving data to/from a memory cell on a column selected by column decoder CDA; and a data path DPB for supplying/receiving data to/from a memory cell on a column selected by column decoder CDB. Data paths DPA and DPB each include data input circuitry (an input buffer and a write buffer) and data output circuitry (an output buffer and a preamplifier).
Sub-memory arrays SMA0 and SMA1 constitute a bank BA#1 and sub-memory arrays SMA2 and SMA3 constitute a bank BA#0. A main control circuit MCK is provided in common to banks BA#1 and BA#0 and receives an address signal ADD and a command CMD instructing a operating mode in synchronization with a clock signal CLK to generate an operation control signal for banks BA#0 and BA#1.
The semiconductor memory device is a clock synchronous semiconductor memory device operating in synchronization with clock signal CLK, a control signal and an address signal are supplied in synchronization with clock signal CLK and data DQ is transferred in synchronization with clock signal CLK.
A sub-control circuit SCK0 is provided to bank BA#0 and a sub-control circuit SCK1 is provided to bank BA#1.
A main control circuit MCK generates an operation control signal for a bank designated according to a bank address included in address signal ADD. Sub-control circuits SCK0 and SCK1 each generate a control signal for performing a designated operation according to a main operation control signal from main control circuit MCK. Each of sub-control circuits SCK0 and SCK1 operates according to an operation control signal from main control circuit MCK independently of the other.
By dividing a memory array into two banks BA#0 and BA#1 as shown in FIG. 24, banks BA#0 and BA#1 can be activated/deactivated independently of each other by sub-control circuits SCK0 and SCK1. Activation of a bank indicates a state that a memory cell row is placed in a selected state in the bank. By making a data access in an interleaved manner to banks BK#0 and BK#1, a high speed access can be achieved without a penalty on page switching.
FIG. 25 shows a configuration of sub-memory arrays SMA0 to SMA3 shown in FIG. 24 schematically. Sub-memory arrays SMA0 to SMA3 are of the same configuration, and therefore, in FIG. 25, there is representatively shown one sub-memory array SMA.
In FIG. 25, sub-memory array SMA includes: a plurality of memory blocks MB0 to MB7; sense amplifier bands SAB1 to SAB7 each placed between adjacent two memory blocks of memory blocks MB0 to MB7 and sense amplifier bands SAB0 and SAB8 placed outside the respective memory blocks MB0 and MB7.
Memory cells are arranged in rows and columns in each of memory blocks MB0 to MB7. Sense amplifying circuits are provided corresponding to memory cell columns of memory blocks MB0 to MB7 in sense amplifier bands SAB0 to SAB8. Sense amplifier bands SAB0 to SAB8 are arranged in a so-called xe2x80x9calternate arrangement type shared sense amplifier configurationxe2x80x9d, in which sense amplifying circuits are arranged alternately on both sides of columns in a corresponding memory block and each sense amplifying circuit is shared between adjacent blocks.
In a sub-memory array SMA, a row select operation is performed in units of blocks. A memory block is designated by a block select signal generated according to a block address signal included in address signal ADD, and row selection is performed in the designated memory block.
One or two memory blocks are designated at a time. In a case where two memory blocks are simultaneously designated, one memory block is selected among 4 memory blocks in the upper side and one of 4 memory blocks in the lower side is selected. Memory blocks sharing a sense amplifier band are not selected simultaneously.
As sub-memory array SMA is divided into a plurality of memory blocks MB0 to MB7, sub-control circuits SCK0 and SCK1 each are divided into local control circuits corresponding to respective memory blocks MB0 to MB7.
In sub-memory array SMA, as shown in FIG. 25, partial activation operation (activation in a block basis) is performed with non-selected memory blocks maintained in a precharge state, reducing a current consumption.
Sub-memory arrays SMA shown in FIG. 25 are arranged in each of banks BA#0 and BA#1. Therefore, at a boundary between banks BA#0 and BA#1, sense amplifier band SAB8 of bank BA#1 and sense amplifier band SAB0 of bank BA#0 abut on each other. Banks BA#0 and BA#1 share no sense amplifier band and the sense amplifier bands of these banks BA#0 and BA#1 can be activated and deactivated independently of each other.
FIG. 26 is a diagram schematically showing sub-control circuits SCK0 and SCK1 shown in FIG. 25 schematically. Sub-memory array SMA2 included in bank BA#0 includes memory blocks MB00 to MB07. Sub-memory array SMA0 included in bank BA#1 includes memory blocks MB10 to MB17. Sense amplifier bands are arranged on both sides of each of memory blocks MB00 to MB07 and on both sides of each of memory blocks MB10 to MB17. In FIG. 26, there are shown sense amplifier bands each with a rectangular region.
Sub-control circuit SCK0 includes local control circuits LCK00 to LCK07 provided corresponding to respective memory blocks MB00 to MB07 and sub-control circuit SCK1 includes local control circuits LCK10 to LCK17 provided corresponding to respective memory blocks MB10 to MB17.
Main control circuit MCK generates a row-related control signal group BRC and a predecode block address PBA for each bank according to a command CMD and address signal ADD externally applied and further generates an internal clock CLK in synchronization with an external clock signal ECLK. Internal clock CLK from main control circuit MCK is applied commonly to local control circuits LCK00 to LCK07 and LCK10 to LCK17.
Row-related control signal group BRC specific to each bank includes a row-related control signal BR0 for bank BA#0 and a row-related control signal BR1 for bank BA#1. Row-related control signal BR0 is applied commonly to local control circuits LCK00 to LCK07 and row-related control signal BR1 is applied commonly to local control circuits LCK10 to LCK17.
Predecode block address signal PBA is generated by predecoding a block address included in external address ADD. Since banks BA#0 and BA#1 each include 8 memory blocks, predecode block address PBA of 6 bits is generated. Predecode address signal of 2 bits designates the upper half or lower half of memory blocks of each of banks BA#0 and BA#1 and predecode signal PBG1 of the remaining 4 bits designates one memory block in the memory blocks in each of the upper half and lower half. Therefore, one bit out of each of predecode block address PBG0 and PBG1 is applied to a respective one of local control circuits LCK00 to LCK07 and LCK10 to LCK17.
In banks BA#0 and BA#1, memory blocks are designated by common predecode block address PBA. A row-related signal for a bank designated by a bank address included in bank address ADD is activated by row-related control signal group BRC specific to the bank, and an operation related to row selection is performed.
Note that in FIG. 26, there is shown no configuration of sub-memory arrays SMA1 and SMA3, for the sake of simplification of the drawing. Sub-memory arrays SMA1 and SMA3 have a configuration similar to that of sub-memory arrays SMA0 and SMA2 and a row select operation is controlled by local control circuits LCK00 to LCK07 and LCK10 to LCK17.
Data paths DPA and DPB each, as described above, include: a write driver performing writing of data into a selected memory cell; a preamplifier amplifying data of a selected memory cell; and a data input-output buffer performing supply/reception of external data, and perform supply/reception of internal data to/from a memory cell on a column selected by column decoder CDA.
By performing row selection in units of memory blocks in banks BA#0 and BA#1 as shown in FIG. 26, non-selected memory blocks can be maintained in a precharge state, thereby achieving reduced current consumption.
An address signal for designating a word line (hereinafter referred to as a word line address signal) needs to be applied commonly to all memory blocks and therefore, applied commonly to local control circuits LCK00 to LCK07 and LCK10 to LCK17.
FIG. 27 is a diagram showing an example of configuration of an input buffer included in main control circuit MCK. In main control circuit MCK, command CMD and address signal ADD externally applied are taken-in in synchronization with external clock signal ECLK (internal clock signal CLK).
In FIG. 27, an input buffer IB includes: an inverter IV inverting clock signal (internal clock signal) CLK; a transmission gate XF1 turning conductive when clock signal CLK is at L level to pass an input signal IN therethrough; an inverter latch IL1 latching a signal passing through transmission gate XF1; a transmission gate XF2 turning conductive when clock signal CLK is at H level to pass a signal latched by inverter latch IL1 therethrough; and an inverter latch IL2 latching a signal passing through transmission gate XF2 to generate internal output signal OUT.
Transmission gates XF1 and XF2 are CMOS transmission gates and are rendered conductive/non-conductive in synchronization with clock signal CLK and a complementary clock signal from inverter IV. Now, description will be given of an operation in input buffer IB shown in FIG. 27 with reference to a signal waveform diagram shown in FIG. 28.
When clock signal CLK is at L level, transmission gate XF1 is in a conductive state and input signal IN is latched by inverter latch IL1. On the other hand, transmission gate XF2 is in a non-conductive state to keep output signal OUT unchanged.
When clock signal CLK rises to H level, transmission gate XF1 enters a non-conductive state and input signal IN exerts no influence on a latch signal of inverter latch IL1. Concurrently with that clock signal CLK rises to H level, transmission gate XF2 enters a conductive state to transmit a signal latched by inverter IL1 to inverter latch IL2 and to generate output signal OUT. Therefore, output signal OUT changes in synchronization with a rise of clock signal. Output signal OUT is maintained in that state during one clock cycle time of clock signal CLK.
Input buffer IB shown in FIG. 27 is provided to each of address signal ADD and command signal CMD in main control circuit MCK. Therefore, since an internal signal is generated in synchronization with a rise of clock signal CLK, the internal signal changes in synchronization with a rise of clock signal CLK if a set-up/hold time relative to clock signal CLK is secured, and therefore, no consideration is required to be given on a skew between input signals, thereby enabling an internal operation start timing to be faster.
FIG. 29 is a diagram schematically illustrating interconnection line loads of an internal clock signal, a row-related control signal and a predecode block address. In FIG. 29, internal clock CLK is transmitted through a signal line SGL0 by a clock driver DRV0. Row-related control signal BR (BR0 or BR1) is transmitted through a signal line SGL1 by drive circuit DRV1. Predecoded block address signal PB is transmitted through a signal line SGL2 by a drive circuit DRV2.
Internal clock signal CLK, as shown in FIG. 26, is required to be applied commonly to local control circuits LCK00 to LCK07, and LCK10 to LCK17, which makes a load capacitance C0 of signal line SGL0 the largest.
As for row-related control signal BR, since all the local control circuits of a corresponding bank are coupled thereto, a load capacitance C1 of signal line SGL1 becomes a second largest.
As for predecode block address bit group PBG1 of predecode block address signal PBA, local control circuits only for two memory blocks are connected thereto in each bank, which makes a load capacitance of the signal line SGL2 the smallest. As for predecode block address bit group PBG0, only 4 local control circuits are connected thereto in each bank. Therefore, by providing a repeater between banks, a load on driver DRV2 is alleviated and the interconnection load thereon can be reduced to be smaller than that of a row-related control signal.
Since interconnection capacitances C0 to C2 on signal lines SGL0 to SGL2 are different from each other, signal propagation delays are different to thereby cause a skew between signals. Particularly, since the signals are transmitted toward a local control circuit LCK17 located remotely from main control circuit MCR in one-way direction along a column direction, signal propagation times are different between nearest local control circuit LCL00 and farthest local control circuit LCK 17 with respect to main control circuit MCK, and the magnitude of the skew corresponding differ between them.
FIG. 30 is a diagram showing a timing relationship between input signals to local control circuit LCK00 and LCK17, and external clock signal ECLK, address signal ADD and command CMD schematically.
Main signal circuit MCK is supplied with external cock signal ECLK, address signal ADD and command CMD. Address signal ADD and command CMD externally applied are taken-in in synchronization with a rise of external clock ECLK, to generate predecode block address signals PBA and row-related control signals BR (BR0 or BR1).
Local control circuit LCK00 located nearest to main control circuit MCK has the smallest phase difference between internal clock CLK and external clock ECLK. In main control circuit MCK, row-related control signal BR0 and predecode block address signal PBA are generated in synchronization with internal clock CLK and transmitted to local control circuit LCK00.
To local control circuit LCK00, internal clock signal CLK reaches a little behind predecode block address signal PBA and row-related signal BR0 since a interconnection capacitance C0 of signal line SGL0 through which internal clock signal CLK is transmitted is larger. In this case, however, a skew between predecode block address signal PBA and internal clock signal CLK is smaller since lengths of interconnection lines for the signals are short. When local control circuit LCK00 operates in synchronization with internal clock CLK under this timing condition, a set-up time for predecode block address signal PBA is insufficient, and therefore, there is a possibility of occurrence of a malfunction.
For local control circuit LCK17 located at the farthest from main control circuit MCK, on the other hand, a propagation time of internal clock signal CLK is the largest because of a long interconnection length. While propagation times of row-related control signal BR1 and predecode block address signal PBA are also larger as compared with a propagation time for local control circuit LCK00, the propagation times are smaller compared with a delay time of internal clock signal CLK. In this case, a phase difference between predecode block address signal PBA and internal clock signal CLK, that is, a skew, becomes large. Therefore, in local control circuit LCK17, an internal operation start timing cannot be faster, thereby hindering a high speed operation.
If an operation start timing in a local control circuit is set according to a distance from main control circuit MCK, an operation start timing becomes different in each local control circuit from others, resulting in a complicated circuit design. Furthermore, with a faster external clock ECLK, a timing adjustment time therefor becomes shorter, causing timing adjustment to be extremely difficult. Accordingly, an operation timing of an internal circuit needs to be set according to the worst skew condition for local control circuit LCK located at the farthest from main control circuit MCR, leading to a problem that a high speed operation is hindered.
Furthermore, in predecode block address signal PBA as well, predecode block address signal bit group PBG0 and predecode block address bit group PBG1 are different in interconnection load from each other, causing a difference in delay time. Therefore, timings at which predecode block address signal bits all becomes a definite state are different in local control circuits from each other, thereby causing a case where a correct decoding operation is not performed.
FIG. 31 is a diagram schematically showing a configuration of main control circuit MCK. In FIG. 31, main control circuit MCK includes: a clock buffer 900 receiving external clock ECLK to generate internal clock CLK; a command input buffer 902 taking in a command CMD externally applied in synchronization with internal clock signal CLK from clock buffer 900; a row address input buffer 904 taking in address signal ADD externally applied in synchronization with internal clock CLK; a row-related control signal generating circuit 905 decoding command CMD from command input buffer 902 in synchronization with internal clock signal CLK to generate row-related control signal BR0 for bank BA#0 according to a result of decoding; a row-related control signal generating circuit 906 decoding command CMD from command input buffer 902 in synchronization with internal clock signal CLK to generate row-related control signal BR1 for bank BA#1 according to a result of decoding; and a column-related control circuit 908 decoding command CMD from command input buffer 902 in synchronization with internal clock CLK to control operations in circuitry related to a data access (column selection and data input/output).
Bank address BAD from row address input buffer 904 is applied to row-related control signal generating circuits 905 and 906, and a row-related control signal generating circuit provided to a bank designated by the bank address BAD is activated. Row-related control signal BR0 for bank BA#0 includes: a row address decode enable signal RADE less than 00 greater than , a word line drive timing signal RXT less than 0 greater than , a bit line isolation instructing signal BLI less than 0 greater than , a bit line equalize instructing signal BLEQ less than 0 greater than , and sense amplifier activating signals SON less than 0 greater than  and SOP less than 0 greater than . Likewise, row-related control signal BR1 for bank BA#1 includes: signals RADE less than 1 greater than , RXT less than 1 greater than , BLI less than 1 greater than , BLEQ less than 1 greater than , SON less than 1 greater than  and SOP less than 1 greater than .
In FIG. 31, column-related control circuit 908 is shown controlling a data path DP performing input/output of data. However, an operation of column decoders provided to banks BA#0 and BA#1 are also controlled by column-related control circuit 908.
In main control circuit MCK, as shown in FIG. 31, there are provided row-related control signal generating circuits 905 and 906 corresponding to the respective banks BA#0 and BA#1. Therefore, with increase in the number of banks, the number of row-related control signal generating circuits needs increasing and in response, a need arises for modifying a layout of row-related control signal generating circuits in main control circuit MCK. For this reason, main control circuit MCK needs to be redesigned according to a bank configuration. Moreover, in a case where loads of signal lines are changed in the redesign, a redesign for adjusting a skew among signals is further required. Accordingly, there arises a problem that it is difficult to adapt to a change in bank configuration. Furthermore, with increase in the number of banks, the number of row-related control signal generating circuits increases, and in response, the number of signal lines transmitting row-related control signals increases to cause not only increase in interconnection region but also increase in circuit occupation area, thereby causing a problem of an increased chip size.
Row-related control signal generating circuits each generate row-related control signals in a prescribed sequence in synchronization with clock signal CLK. When clock signal CLK is of high speed, a pulse width of a control signal generated internally is determined by a cycle time of clock signal CLK. When an internal control signal is generated as a pulse signal, the signal has an H level period and an L level period. In order to generate a pulse signal of a correct waveform, it is necessary to secure an H level period and L level of the pulse signal.
In a case where a main control signal is transferred to local control circuits through bus drive circuits as shown in FIG. 29, a rise time and fall time of a main control signal are determined by operating characteristics of a bus driver and load capacitance of the bus. Therefore, when local control signals are generated utilizing a rise and fall of the main control signal, an activation timing of a local control signal generated in a local control circuit is determined by a restrictive condition imposed on a pulse width of the main control signal, to cause a case of disabling a high speed operation. Therefore, an internal operation cannot be performed according to a high speed clock signal, thereby causing a problem of disabling a data access in synchronization with a high speed clock signal.
It is an object of the present invention to provide a semiconductor integrated circuit device capable of correctly operating in synchronization with a high speed clock signal.
It is another object of the present invention to provide a semiconductor integrated circuit device capable of performing a selecting operation of a memory cell at a high speed in synchronization with a high speed clock signal, without an influence of a skew among signals.
It is still another object of the present invention to provide a semiconductor integrated circuit device capable of correctly operating according to a high speed clock signal while being easily adapting to a change in bank configuration.
It is yet another object of the present invention to provide a semiconductor integrated circuit device capable of correctly activating/deactivating a plurality of internal memory cell select operation control signals in a prescribed sequence at short intervals.
It is a further object of the present invention to provide a semiconductor integrated circuit device capable of correctly generating a local control signal without suffering a restraint on a pulse width of a main control signal.
A semiconductor integrated circuit device according to a first aspect of the present invention includes: a main control signal generating circuit generating a plurality of control signals having different phases from each other according to an operating mode instructing signal externally applied. The main control signal generating circuit activates one of plural sets of main control signals in a prescribed sequence according to the operating mode instructing signal. The plural sets of main control signals are selected in a prescribed sequence.
The semiconductor integrated circuit device according to the first aspect of the present invention further includes: a local control signal generating circuit generating local control signals in accordance with main control signals from the main control signal generating circuit. The local control signal generating circuit receives main control signals of sets different from each other, to generate local control signals in response to different directions of changes of main control signals of different sets.
A semiconductor integrated circuit according to a second aspect of the present invention includes: a plurality of local circuits each performing a designated operation when active; and a main control signal generating circuit provided commonly to the plurality of local circuits to generate a plurality of control signals having different phases from each other in accordance with an operating mode instructing signal externally applied. The main control signal generating circuit drives plural sets of main control signals at a prescribed sequence in accordance with the operating mode instructing signal.
The semiconductor integrated circuit device according to the second aspect of the present invention further includes: local control circuits provided corresponding to the respective local circuits and generating local operation control signals for the corresponding local circuits in accordance with main control signals from the main control signal generating circuit. The local control circuit receives main control signals of sets different in phase from each other to generate local control signals in response to different directions of changes of main control signals of different sets. The main control signal generating circuit drives one of the plural sets each including a plurality of main control signals to a selected state in a prescribed sequence in accordance with an operating mode instructing signal.
Plural sets of main control signals are activated in units of sets in accordance with an operation mode instructing signal, and local control signals are generated in accordance with change in main control signals in different sets of main control signals. Main control signals can be generated to be transmitted to the local control circuits with the pulse width of the main control signals sufficiently secured. Specifically main control signals in different sets are utilized to eliminate the need of changing the main control signals in each set at high speed, and an internal operation would not be rate-determined by the changing rate of the main control signals in each set. Thus, local control signals can be generated at high speed to speed up an internal operation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.